1. Field of the Invention
The present invention relates to a semiconductor device consisting of P-channel and N-channel thin-film transistors arranged on the same substrate and also to a method of fabricating such a semiconductor device. More particularly, the invention relates to a CMOS circuit configuration composed of thin-film transistors formed on a glass substrate and also to a method of fabricating this CMOS circuit configuration.
2. Description of the Related Art
A technique for fabricating a thin-film transistor (TFT) by growing a thin film of silicon on a glass substrate is known. This technique has been developed to fabricate active matrix liquid crystal displays.
A liquid crystal display comprises a pair of glass substrates together with a liquid crystal material held between the substrates. A large number of pixels are arranged in rows and columns. For each pixel, an electric field is applied across the liquid crystal material to vary its optical property. Thus, an image is displayed.
In the active matrix liquid crystal display, a TFT is disposed at each of the pixels arranged in rows and columns as described above. This TFT controls electric charge going into and out of the pixel electrode.
In the present technology, a peripheral driver circuit for driving hundreds of TFTs X hundreds of TFTs arranged in the active matrix region is composed of an IC circuit (known as a driver IC) attached to the outside of a glass substrate by TAB (tape automated bonding) or other technique.
However, mounting driver IC to the outside of the glass substrate complicates the manufacturing process. Also, the driver IC results in unevenness. This hinders wide application of the liquid crystal display incorporated in various electronic appliances.
A technique for solving these problems consists of fabricating the peripheral driver circuit out of TFTs and integrating these TFTs with other TFTs on the glass substrate. This makes the whole system a unit. Furthermore, the process sequence is simplified, the reliability is enhanced, and the application can be extended.
In this active matrix liquid crystal display incorporating the peripheral driver circuit as described above, CMOS circuits are necessary to form the peripheral driver circuit. A CMOS circuit is a complementary combination of an N-channel transistor and a P-channel transistor, and is one of fundamental configurations of electronic circuits. The following various methods for fabricating CMOS configuration out of TFTs on a glass substrate are known.
One known method is illustrated in FIGS. 4(A)-4(D). As shown in FIG. 4(A), a silicon oxide film 402 acting as a buffer layer is first formed on a glass substrate 401. An active layer, 403 and 404, made of crystalline or amorphous silicon is formed on the silicon oxide film 402. A silicon oxide film 405 serving as a gate-insulating film is coated on the laminate. The active layer portion 403 is an island of region forming an active layer for an N-channel TFT. The active layer portion 404 is an island of region forming an active layer for a P-channel TFT.
After obtaining the state shown in FIG. 4(A), gate electrodes 406 and 407 are fabricated out of silicide or other material (FIG. 4(B)).
Then, as shown in FIG. 4(C), phosphorus (P) ions are implanted while masking the other TFT region with a resist mask 408. As a result, a source region 409, a drain region 411, and a channel formation region 410 for the N-channel TFT are formed by self-aligned technology.
Thereafter, as shown in FIG. 4(D), the resist mask 408 is removed. A new resist mask 412 is placed. At this time, boron (B) ions are implanted. By this manufacturing step, a source region 415, a drain region 413, and a channel formation region 414 for the P-channel TFT are formed by self-aligned technology.
In this way, the N-channel and P-channel TFTs can be formed simultaneously on the same glass substrate. In the configuration shown in FIGS. 4(A)-4(D), the drain region 411 of the P-channel TFT is connected with the drain region 413 of the N-channel TFT. The gate electrodes of both TFTs are connected together. Consequently, a CMOS configuration is obtained.
The manufacturing steps shown in FIGS. 4(A)-4(D) are the most fundamental processes for CMOS circuits. However, two separate masks 408 and 412 used for implantation of dopant ions for imparting N-type conductivity and P-type conductivity, respectively, are necessary. This complicates the process sequence. That is, the two resist masks 408 and 412 are necessitated during the dopant ion implantation.
In order to form each resist mask, a resist material must be applied, sintered, selectively exposed, using a photomask, and selectively removed for formation of the resist mask. Furthermore, where dopant ions are implanted, using a resist as a mask, the resulting ion bombardment modifies the quality of the resist. This makes it difficult to remove the resist mask.
Where the manufacturing steps illustrated in FIGS. 4(A)-4(D) are adopted, it follows that two manufacturing steps for removing the resist material which has been modified in quality and thus is difficult to remove are performed. This will be another factor of defects. Hence, these two steps are undesirable.
A known method of alleviating this problem is illustrated in FIGS. 5(A)-5(D). As shown in FIG. 5(A), a silicon oxide film 502 is formed as a buffer layer on the glass substrate 401. An active layer, 503 and 504, of crystalline or amorphous silicon is formed on the silicon oxide film 502. A silicon oxide film 505 acting as a gate-insulating film is formed over the laminate. The active layer portions 503 and 504 are islands of regions forming active layers for N- and P-channel TFTs, respectively. Then, gate electrodes 506 and 507 of silicide or other material are formed, thus giving rise to a state shown in FIG. 5(B).
Under this condition, phosphorus (P) ions are implanted into the whole surface. As a result, N-type regions 508, 510, 511, and 513 are formed (FIG. 5(C)). The dose of the P ions is 1xc3x971015 to 2xc3x971015 ions/cm2. The surface dose is 1xc3x971020 ions/cm2 or more.
Then, a resist mask 514 is placed only on selected regions forming an N-channel TFT. Boron (B) ions are implanted at a dose about 3 to 5 times as high as the dose of the aforementioned P ions. The N-type regions 511 and 513 are converted into P-type. In this way, P-channel source region 515, drain region 516, and channel formation region 512 are formed by self-aligned technology.
The heavy doping described above is required because it is necessary that the regions 515, 512, and 516 form an NIN junction. In this manner, N- and P-channel TFTs can be obtained with a fewer number of masks than the configuration shown in FIGS. 4(A)-4(D). In the configuration shown in FIGS. 5(A)-5(D), the N-channel TFT has the source region 508, channel formation region 509, and drain region 510. The P-channel TFT has the drain region 516, channel formation region 512, and drain region 515. Although the configuration shown in FIGS. 5(A)-5(D) has the advantage that it can be manufactured with simplified manufacturing steps, the configuration has the following drawbacks.
First, dopant ions are implanted into the resist mask 514 at a quite high dose. This gives rise to a conspicuous modification of the quality of the resist. This in turn often results in defective manufacturing steps.
Secondly, the right TFT (P-channel TFT) as viewed in FIGS. 5(A)-5(D) has the channel formation region. The drain region adjacent to this channel formation region is a quite heavily doped region. The dose is in excess of the dose necessary for the P-channel type and sufficient for type-conversion. Therefore, the off current near the junction between the channel formation region and the drain region is negligible.
Thirdly, ions take unstraight paths, thus introducing B ions into the channel formation region 512. As a consequence, required characteristics cannot be obtained.
Fourthly, implanting dopant ions at a high dose imposes heavy burden on the ion implanter and on the plasma implant machine. Also, much labor is required to decontaminate the inside of the machine and to service the machine. In this way, various problems take place.
Fifthly, introducing dopant ions at a high dose increases the processing time.
Sixthly, where annealing is carried out with laser light, difficulties occur. After the step shown in FIG. 5(D), the resist mask 514 is removed. Then, an annealing step for activating the implanted dopants and annealing the doped regions with laser irradiation is necessary. This method is useful where a glass substrate having poor heatproofness is used. At this time, the regions 515 and 516 are more severely deteriorated in crystallinity than the regions 508 and 510, because the regions 516 and 516 are more heavily doped than the regions 508 and 510. Therefore, the regions 508 and 510 differ greatly from the regions 515 and 516 in dependence of light absorption coefficient on wavelength. Under this condition, the annealing effect of the laser irradiation differs materially between these two kinds of regions. Consequently, the left N-channel TFT and right P-channel TFT have greatly different characteristics with undesirable results.
It is an object of the present invention to provide techniques for circumventing the problem occurring when N- and P-channel TFTs are fabricated at the same time, i.e., increase in the number of masks, and the problem with the steps illustrated in FIGS. 5(A)-5(D), i.e., high-dose dopant ion implantation.
Specifically, the invention is intended to provide techniques for fabricating both N- and P-channel TFTs on a glass substrate at a lower cost and with a reduced amount of labor than heretofore and with high reliability.
It is another object of the invention to provide a method of fabricating a CMOS circuit out of TFTs in such a way that the CMOS circuit has high characteristics by compensating for the differences in characteristics between the N- and P-channel TFTs.
One embodiment of the present invention is a semiconductor device comprising an N-channel thin-film transistor and a P-channel thin-film transistor having source and drain regions, said N-channel and P-channel thin-film transistors being integrated on a common substrate. Lightly doped drain (LDD) regions are formed selectively only in the N-channel thin-film transistor. The source and drain regions of the P-channel thin-film transistor are doped with P-type and N-type dopants at first and second doses, respectively. The first dose is higher than the second dose.
A specific example of this configuration is shown in FIG. 3(B), where an N-channel TFT (NTFT) located on the left side and a P-channel TFT (PTFT) located on the right side together form a CMOS circuit. This configuration is characterized in that a lightly doped drain (LDD) region 123 is formed selectively only in the NTFT. This LDD region 123 is located between the channel formation region and the drain region. This LDD region mitigates the electric field intensity between the channel formation region and drain region, thus reducing the off current and suppressing deterioration. Furthermore, the LDD region increases the resistance between the source and drain so that the effective mobility of the TFTs is reduced.
The configuration shown in FIG. 3(B) is similar to the configuration shown in FIG. 2(B) except that a dopant (P) for imparting conductivity N-type is introduced also in the right P-channel TFT. In order that the TFT finally act as a P-channel device, the source and drain regions of the right P-channel TFT are more heavily doped with a P-type dopant than an N-type dopant. For this purpose, B ions are implanted during a step illustrated in FIG. 2(C).
Where silicon is used as a semiconductor, phosphorus (P) is a typical example of the N-type dopant which imparts conductivity N-type. Also, where silicon is used as a semiconductor, boron (B) is a typical P-type dopant.
Where the configuration shown in FIG. 3(B) is employed, those portions in the source and drain region of the P-channel TFT which are adjacent to the channel formation region are more lightly doped with the N-type dopant than other portions. The concentration of the P-type dopant is uniform or substantially uniform over the whole source and drain regions, because P ions imparting conductivity N-type are implanted in the steps shown in FIGS. 1(E) and 2(B), respectively. More specifically, regions 125 and 128 are implanted with P ions twice, but regions 126 and 127 are implanted with dopant ions only once. As a result, the regions 126 and 127 adjacent to the channel formation regions 131 are doped with P ions more lightly than the source region 128 and drain region 125.
On the other hand, the dopant ions imparting the conductivity P-type are implanted only once, as shown in FIG. 2(C). Therefore, the source and drain regions are wholly doped with the P-type dopant uniformly or nearly uniformly.
Another embodiment of the invention is a semiconductor device comprising: an active matrix region formed on a substrate and consisting of thin-film transistors arranged in rows and columns; a peripheral driver circuit for driving said thin-film transistors in said active matrix region, said peripheral driver circuit being formed on said substrate; N-channel thin-film transistors having LDD or offset gate regions and arranged in said active matrix region; complementary N- and P-channel thin-film transistors arranged in said peripheral driver circuit; LDD regions or offset gate regions formed selectively in the N-channel thin-film transistors arranged in said peripheral driver circuit; and said P-channel thin-film transistors arranged in said peripheral driver circuit having source and drain regions doped with an N-type dopant imparting conductivity N-type.
A further embodiment of the invention is a semiconductor device comprising: an active matrix region formed on a substrate and consisting of thin-film transistors arranged in rows and columns; a peripheral driver circuit for driving said thin-film transistors in said active matrix region, said peripheral driver circuit being formed on said substrate; P-channel thin-film transistors arranged in said active matrix region; complementary N- and P-channel thin-film transistors arranged in said peripheral driver circuit; LDD regions or offset gate regions formed selectively in the N-channel thin-film transistors arranged in said peripheral driver circuit; and said P-channel thin-film transistors arranged in said active matrix region and in said peripheral driver circuit having source and drain regions doped with an N-type dopant imparting conductivity N-type.
A yet other embodiment of the invention is a method of fabricating a semiconductor device consisting of N-channel and P-channel thin-film transistors integrated on a common substrate, said method comprising the steps of: forming gate electrodes out of a material capable of being anodized, said gate electrodes having side surfaces; selectively forming a porous anodic oxide film on the side surfaces of said gate electrodes; implanting an N-type dopant, using said anodic oxide film as a mask, at a first dose; removing said anodic oxide film; implanting an N-type dopant, using said gate electrodes as a mask, at a second dose to form LDD regions under which said anodic oxide film existed; and implanting a P-type dopant while masking only those regions which should become the N-channel thin-film transistors.
Specific examples of the above-described structure are given below. FIG. 1(D) shows a manufacturing step for forming a porous anodic oxide film, 112 and 113, selectively on side surfaces of gate electrodes made of a material that can be anodized. FIG. 1(E) shows a step for introducing an N-type dopant, using the aforementioned anodic oxide film as a mask. FIG. 2(A) shows a state obtained after the anodic oxide film has been removed. FIG. 2(B) illustrates a step for introducing an N-type dopant, using the gate electrodes 11 as a mask and forming LDD regions under regions 123 where the anodic oxide film existed. FIG. 2(C) shows a manufacturing step for selectively masking those regions which should become N-channel TFTs and implanting a P-type dopant.
A method of fabricating a semiconductor device consisting of N-channel and P-channel thin-film transistors integrated on a common substrate in accordance with the present invention comprises the steps of: forming gate electrodes out of a material capable of being anodized, said gate electrodes having side surfaces; selectively forming a porous anodic oxide film having a thickness on the side surfaces of said gate electrodes; implanting an N-type dopant, using said anodic oxide film as a mask; removing said anodic oxide film; implanting a P-type dopant while masking only regions which should become the N-channel thin-film transistors; and forming offset gate regions selectively in the N-channel thin-film transistors, said offset gate regions being determined by the thickness of said porous anodic oxide film.
This method is characterized in that, as shown in FIGS. 6(A)-6(D), offset gate regions 613 and 614 are formed so as to have a thickness equal to the thickness of a porous anodic oxide film 605. If a dense anodic oxide film 600 is thick, this also contributes to formation of the offset gate regions.
Other objects and features of the invention will appear in the course of the description thereof, which follows.